Magnetic and optical disk storage devices are commonly used by host computer systems to store large amounts of digital data in a non-volatile manner. Typically, a disk storage medium spinning within the storage device is partitioned into a number of radially spaced concentric or spiral data tracks, where each data track is further partitioned into a number of data sectors. To write and read data to and from a target data sector on a particular track, a recording head (read/write head) is positioned over the track by an electromechanical serving mechanism. Then, to write to the track, the data serves to modulate a current in a write coil or intensity of a laser beam of the recording head in order to write a sequence of corresponding magnetic flux or optical transitions onto the surface of the disk. To read this recorded data, the recording head again passes over the track and emits an analog read signal comprising a sequence of polarity alternating pulses induced by the transitions representing the recorded data. These pulses are then detected and decoded into an estimated data sequence by a read channel and, in the absence of errors, the estimated data sequence matches the recorded data sequence.
A conventional data path in a disk storage system is shown in FIG. 2. User data from a host system is transmitted to a disk controller 2 where it is stored in a data buffer 4. The data buffer 4 may perform a conventional disk caching function depending on its size. The user data is read from the data buffer 4 (as arbitrated by controller 6) and then written to the disk using write/read circuitry 9 in a synchronous read channel 8. As it is written to the disk, a redundancy generator 10 processes the user data to generate redundancy symbols which are appended to the user data to form a code word of an error correcting code (ECC). The Reed-Solomon code is the most common error correcting code employed in disk storage devices currently on the market. The above referenced U.S. Pat. No. 5,446,743 entitled "COEFFICIENT UPDATE METHOD AND APPARATUS FOR REED-SOLOMON DECODER" illustrates one possible embodiment of an ECC encoder/decoder that could be employed in the present invention.
The synchronous read channel 8 typically comprises a channel encoder 11 for encoding the ECC code words according to a channel code before writing the data to the disk. The channel code may implement a simple run-length limited (RLL) code, such as a conventional RLL (d,k) code, and possibly a more complex code, such as a spectral shaping code or a trellis code. The RLL (d,k) code constrains to d the minimum distance in "bit cells" between consecutive transitions (i.e., the minimum number of "0" bits that must occur between consecutive "1" bits), and constrains to k the maximum distance in "bit cells" between consecutive transitions (i.e., the maximum number of consecutive "0" bits). The d constraint mitigates the interference between consecutive transitions known as partial erasure, and the k constraint ensures that sufficient timing information can be extracted to maintain proper bit synchronization during a read operation (i.e., proper self-clocking).
Upon read back, write/read circuitry 9 detects an estimated binary sequence from samples of the analog read signal, and a sync detector 12 symbol synchronizes the data stream (i.e., delineates the symbol boundaries) by detecting a sync mark in the estimated binary sequence. Once symbol-synchronized, a channel decoder 13 decodes the estimated binary sequence according to the reverse operation of the channel encoder 11, thereby generating detected ECC code words which may or may not contain symbols in error. The detected code words are then transferred to the disk controller 2 and stored in the data buffer 4. Typically, ECC syndromes are also generated by a syndrome generator 10 as the detected code words are transferred from the read channel. An error detection and correction circuit 15 processes the ECC syndromes to detect and correct errors in the code words, and the corrected user data portion of the code words is then transferred to the host system.
It is well known that the amount of error propagation that can occur when decoding the channel code can impact significantly the effectiveness of the ECC decoder. It is also well known that in decoding the channel code the amount of error propagation tends to grow exponentially as the realized code rate approaches the theoretical capacity (Shannon capacity) of the coding constraints. Thus, the conventional data path of FIG. 2 has precluded the use of longer channel block codes with code rates closer to the theoretical capacity in order to minimize error propagation.
A paper published in the IBM Technical Disclosure Bulletin, Vol. 23, No. 10, March 1981, entitled "CIRCUITRY FOR PERFORMING ERROR CORRECTION CALCULATIONS ON BASEBAND ENCODED DATA TO ELIMINATE ERROR PROPOGATION," discloses a method for performing error correction on the channel encoded data in order to avoid the above described error propagation that occurs if the error correction is performed on the decoded data as in FIG. 2. This technique enables the use of significantly longer channel block lengths (and significantly higher code rates) because errors are corrected before decoding. Conceptually, the user data is encoded using a first channel code (e.g., RLL (d,k)), and the channel encoded data encoded according to an ECC code, such as a Reed-Solomon code. The ECC redundancy generated by the ECC code will typically not satisfy the constraints of the first channel code and, therefore, must be re-encoded using a second channel code with low error propagation (i.e., with a lower code rate) before writing the data to the disk. Upon read back, the ECC redundancy symbols are first decoded using the second channel code, and then used to correct errors in the encoded user data. The corrected user data is then decoded using the first channel code and transferred to the host system. Error propagation does not occur in the decoding process since the user data is corrected before decoding. The present invention discloses various improvements to this basic idea, and overcomes certain problems not currently addressed by the prior art.
One aspect of the present invention concerns timing recovery and, in particular, the problem presented by a long k constraint in a RLL (d,k) channel code. As described in greater detail below, timing recovery in synchronous read channels is typically implemented by synchronizing the sampling of the analog read signal using a variable frequency oscillator (VFO) in a phase-lock loop (PLL). Synchronously sampling the analog read signal typically requires a relatively short k constraint due to the noise sensitivity and fabrication variances of the VFO. However, it is difficult to construct long code words and thereby achieve higher code rates with a short k constraint.
In another aspect of the present invention, the synchronous read channel employs sub-sampling (sampling significantly below the baud rate) together with a channel code that minimizes the bit error rate in the presence of sub-sampling. The sub-sampling channel code can be constructed using a long block length and thereby achieve an efficient code rate because the above described error propagation in the channel decoder is avoided.
Another aspect of the present invention is to modify the read channel detection algorithm according to the code constraints of the first and second channel codes for encoding the user data and redundancy symbols, respectively, in order to minimize the bit error rate in the detected data sequence.
Still another aspect of the present invention is to improve the symbol synchronization function of the storage system through the use of multiple synchronization marks together with retroactive and split-segment symbol synchronization.